By Scooter D. Johnson, Postdoctoral Fellow | US Naval Research Laboratory
The drive toward miniaturization of devices such as computers and cellular phones has pushed the limits of component design and materials engineering to smaller sizes and more efficient power consumption. One such component that still requires a relatively large footprint is the embedded inductor.
A solution for reducing the inductor size is to replace the air-core with a magnetic material. This is accomplished by fabricating inductors on top of a single-plane, or sandwiched between a double-plane, of a magnetic material, such as Ni-Fe, Co-Zr-Ta, Co-Nb-Zr, or Co-Hf-Ta-Pd. These materials are chosen for their high permeability and low-melting temperature, which enables integration into a system-on-chip process by conventional deposition techniques, for example, rf sputtering. However, the low resistivity of these materials requires additional fabrication steps to decrease eddy current loss and to insulate the plane from the conductor. These steps involve deposition of an oxide or polyimide layer between the conductor and plane and/or fabricating the ground-plane in a slotted pattern. There have also been efforts to utilize higher resistivity magnetic materials that could bypass the additional fabrication steps. For example, yttrium iron garnet (Y3Fe5O12) (YIG) has been employed in the study of improving integrated planar inductor performance in the 1 MHz to 10 GHz frequency range. A YIG film is coated onto a sapphire or silicon substrate and the copper inductor is electroplated directly onto the YIG using a standard lithography process. While such ferrite-integrated inductors have shown improvement in inductance, making this process compatible with system-on-chip technology still has many obstacles, such as the high melting temperature needed for ferrite preparation (900°C to 1,400°C) .
An alternative approach would be to fabricate the inductor onto the chip then deposit a high permeability material over the inductor, thereby filling the inductor core. Benefits to this approach are that electromagnetic interference is reduced by confining the stray field to the magnetic material, more magnetic material can be incorporated into the inductor core, and the process can be performed as a back-end process after all other device structures have been finalized. However, there are also several challenges to this approach, such as the high-temperature regime of ferrite preparation mentioned above and obtaining a several-micron-thick film to fill the inductor core.
We have begun investigating a relatively new deposition process called aerosol deposition (AD) to deposit ferrite materials for integration into current CMOS processing of system-on-chip technology that we expect will overcome the fabrication challenges discussed above. The AD technique has existed since about 1995; it was developed in Japan and has become a popular tool with researchers in Korea, but until now has been unreported in the US. We have built a simple tool capable of performing AD for less than $100,000 and have been running it for about two years. The AD process is illustrated in Figure 1 as a series of step-by-step drawings of three particles impacting upon a substrate demonstrating the mechanisms of fracture, adhesion, and densification of the film. Figure 1A shows three particles moving toward the substrate with a typical velocity of 100 to 500 m/s. Figure 1B shows the result of impact, fracture and adhesion of the first particle. This anchoring layer provides the mechanical adhesion between the substrate and film. Figure 1C shows the subsequent impact of the second particle upon the first causing fracture, adhesion, and densification of the crystallites. Figure 1D shows the impact of the third particle which works to further compact the underlying film and bond the crystallites. This process continues until the film density reaches greater than 90 percent of the bulk material. AD can produce these dense nano-crystalline films at several microns per minute and can coat films up to several hundred microns thick.
Figure 2 is a scanning electron microscope image of the cross-section of a selected 79-μm-thick YIG film deposited onto sapphire. This film has a density of about 2.6 g/cm3 or 50 percent of the bulk YIG density. We recently reported results of deposition of 39-μm-thick polycrystalline YIG films on sapphire at room temperature by AD. In this work we compared the structural and magnetic properties of the as-deposited film to the the film after a 1,280°C sinter. We found that the as-deposited film matched much more closely to the starting powder than to the sintered film suggesting that the film is behaving as a medium-density nano-crystalline material. Current work is underway to further improve the film density and magnetic properties.
As an initial demonstration of the utility of the AD process we fabricated a single-turn gold inductor onto an alumina substrate and coated it with YIG. Figure 3 shows the inductor design on the left and the final fabricated YIG-filled inductor to the right. S-parameter data were collected between 10 MHz and 10 GHz. We found that the coated inductor achieved a 79 percent improvement in inductance below about 300 MHz without affecting the quality factor.
These early results suggest that AD shows much promise as a tool for creating thick magnetic films onto substrates for integration into on-chip technology. We believe that with some minor improvements in system design and particle classification AD will become a valuable industry tool in the near future.
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About the Author
Dr. Johnson graduated from Lewis & Clark College, Portland, OR with a B.A. in physics in 2005 where his experimental focus was studying the dynamics of dense-core granular transport in hippocampal neurons. He received his Ph.D. in physics from the University of California, Davis in 2011. While at Davis his experimental research focused on understanding the role that dimensionality and magnetic order have on heavy fermion superconductors. He is currently completing his third year as an ASEE Postdoctoral Fellow at the U.S. Naval Research Laboratory in Washington D.C. where he has focused on building and characterizing the first aerosol deposition system in the United States with the goal of coating materials with 50–100 μm thick films for a variety of applications.
This work is sponsored by the Office of Naval Research under program number N0001413WX20845 (Dr. Daniel Green, Program Manager).